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Altera_Forum's avatar
Altera_Forum
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11 years ago

Arriav V FPGA doesn't work.

Hello, everyone :

I have a problem in my design. Arriav V FPGA can download successfully, but it does not work. I use combinational logic to assign 55AA in my VHDL code. After I download it to FPGA, the output of FPGA is always high. I have no idea how to fixed it !

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    entity TEST1

    port (

    TEST_PORT : out std_logic_vector (15 downto 0)

    );

    end TEST1;

    architecture TEST2 of TEST1 is

    begin

    TEST_PORT <= x"55AA" ;

    end TEST2;
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Yes, I check the pin assignments more times. The outputs of FPGA are always 'high'.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Are you sure the device is configuring? I assume you're configuring via JTAG and the Quartus II programmer is confirming that configuration was successful?

    If you can confirm that the device is configuring then check the DEV_OE pin. That pin can be used to tri-state all I/O on the device.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Glad to hear that. Can you share with the forum what the problem was? That may help someone else who runs into the same problem in the future.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    The Power circuit have a problem. The circuit current is not enough to drive FPGA. When we increase circuit current, the problem is fixed.