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Altera_Forum's avatar
Altera_Forum
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11 years ago

Arriav V FPGA doesn't work.

Hello, everyone : I have a problem in my design. Arriav V FPGA can download successfully, but it does not work. I use combinational logic to assign 55AA in my VHDL code. After I download it to FPG...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

entity TEST1

port (

TEST_PORT : out std_logic_vector (15 downto 0)

);

end TEST1;

architecture TEST2 of TEST1 is

begin

TEST_PORT <= x"55AA" ;

end TEST2;