ArriaII transceiver oversampling

Hi,

I don't have a direct answer, but the following comments are relevant to your oversampling question ...

I'm working on a Hittite 20GHz clock rate ADC design, with 10Gbps output lanes. The output lanes use logic levels with a negative offset (common mode), so to interface to an FPGA I need to AC-couple and use PRBS modulation to ensure the DC offset is near zero (the ADC has an XOR modulation port).

The Hittite evaluation board I first received routed a divided-clock (divide-by-16) to the XOR port. This scheme did not work reliably. I've just received a board we designed that allows me to drive the modulation port with a PRBS pattern. I plan on testing the XOR port with 10Gbps, 5Gbps, and 2.5Gbps PRBS patterns, i.e., with a x1 pattern and x2 and x4 undersampled PRBS patterns. If the lower-rate patterns are reliable, I could then generate the PRBS pattern using an Arria or Cyclone device, or a lower-rate PRBS device from TI, rather than needing a 10Gbps capable device (though TI have just released re-timer parts that I might be able to use as a 10Gbps PRBS generator).

Based on my tests with the Stratix IV GX boards (at up to 8Gbps), I would be very reluctant to try oversampling anything more than 4x. I have chatted with engineers that worked on SATA systems, and they have used 6Gbps SATA interfaces to process 1.5Gbps SATA streams, but they indicated that that was about the limit that they could get to successfully work.

If you have the option to modulate the signal you are capturing (using a high-speed XOR gate), then you can create a data stream that toggles at a much higher rate, and could remove the modulation in the FPGA. The way this works is as follows;

1. At power-on, you disable the data source and enable the PRBS (the other input to the XOR gate), resulting in only the PRBS being transmitted.

2. The FPGA receiver CDR locks to the PRBS pattern. Logic internal to the FPGA uses the incoming PRBS data to load (seed) a PRBS generator internal to the FPGA.

3. FPGA logic checks for bit-errors, once you get none, the local PRBS and the remote PRBS are locked.

4. At that point, you enable the data (the other input to the XOR gate). The data being transmitted is then your low-speed serial data stream modulated with the higher-speed PRBS pattern.

5. Inside the receiver FPGA, you XOR the incoming modulated data stream with the local PRBS generator, which demodulates the data, removing the high-speed PRBS pattern.

6. The output of the XOR demodulator is your original (oversampled) low-speed data stream.

7. You can then decimate the data and process it.

I'm not sure if this option is available to you, but its an interesting trick :)

Cheers,

Dave