ArriaGX compile times

Yes, I do have physical synthesis turned on. Unfortunately the altera PCIe IP core (which I'm using in this design) will not meet timing when I turn it off. I have worked with an Altera FSE on this and we can't find any way around this.

I've tried all the normal things to get the compile times down (reducing timing constraints where possible, pipelining my portion of the design, setting the compiler to optimize for speed, etc)..

I appreciate the responses, but would be really interested to know what kind of compile times other users of the ArriaGX are getting...

Thanks,

Frank