Forum Discussion
Yamada1
Occasional Contributor
Occasional ContributorArria10 Embedded Memory
I have a question about Embedded Memory. I plan to use Arria10's M20K block RAM with 2-Port RAM.
In figures 1 and 4 of the user guide, the input signal to the RAM block transitions at the falling e...
Hi,
Check out this document link https://www.intel.com/content/www/us/en/docs/programmable/683240/17-0/about-embedded-memory-ip-cores.html (Page 41) onwards, the Design Example may be can help you as well.
Thanks,
Best Regards,
Sheng
FvM
Super Contributor
Super ContributorGenerally, timing analysis will take care of sufficient hold time. You'll notice that maximal A10 block RAM clock frequency is rather high, e.g. > 500 MHz. Respectively you can expect a low hold time requirement, probably < 1 ns.
Yamada1Occasional Contributor
Occasional ContributorMr. FvM
Thank you for your answer.
It was very helpful.
