Arria10 DDR4 interface deskew limits

Hi IHohm, Please find my feedback below: a) How much total skew difference can be compensated by the deskew calibration shift during DDR4 calibration ? >> Package delays can be different for the same pin in different packages which can affect system timing. Thus, the mismatch observed is expected. If you want to use multiple migratable packages in your system, you should compensate for package skew as described in this chapter “ 2.8.6 Package Migration” (page 124) and make sure both devices compensated correctly and pass timing. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_plan.pdf b) I have seen up to 80ps package delay difference between DDR4 signals. When not ticking the box "Package deskew with board layout" Quartus takes care about package skews internally. Are the package skew differences deskewed using the same FPGA resouces as calibration shift ? >> If you do not enable the package deskew option, the Quartus Prime software will adjust the skews on the appropriate signals using the package delay numbers and we don't need to adjust for the delays with board traces. If you do enable the package deskew option, the Quartus Prime software does not use the package delay numbers for timing analysis, and you must deskew the package delays with the board traces for the appropriate signals for your design. If you want calibration to handle this instead of adjusting your board design, turn the deskew options off. However, Intel recommended to perform package deskew if your operating frequency is equal to 933Mhz and above using DDR4. For more details, you can refer to section 6.4.5 (page 253) in the user guide below. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf I sincerely hope this helps. Thanks Regards, NAli1