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IHohm's avatar
IHohm
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7 years ago

Arria10 DDR4 interface deskew limits

I am designing a DDR4-32bit interface for Arria10.

I will use either a GX220 or a GX270 device with F29 package.

I have to decide to use 'Package deskewed with board layout' or not.

The package delays reported in the pin file for the same signal betwen GX220 and GX270 differ slightly. I checked the dq/dqs pins and found 0 to 14ps delay difference comapring GX220 to GX270.

When I choose to compensate the package skew by external trace length for GX220 and then mounting a GX270, then the HMC has to compensate this 14ps mismatch by shifting the signal durcing calibration.

My question is:

a) How much total skew difference can be compensated by the deskew calibration shift during DDR4 calibration ?

b) I have seen up to 80ps package delay difference between DDR4 signals. When not ticking the box "Package deskew with board layout" Quartus takes care about package skews internally. Are the package skew differences deskewed using the same FPGA resouces as calibration shift ?

Regards Ingmar

3 Replies

  • NurAida_A_Intel's avatar
    NurAida_A_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago
    Hi IHohm, Please find my feedback below: a) How much total skew difference can be compensated by the deskew calibration shift during DDR4 calibration ? >> Package delays can be different for the same pin in different packages which can affect system timing. Thus, the mismatch observed is expected. If you want to use multiple migratable packages in your system, you should compensate for package skew as described in this chapter “ 2.8.6 Package Migration” (page 124) and make sure both devices compensated correctly and pass timing. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_plan.pdf b) I have seen up to 80ps package delay difference between DDR4 signals. When not ticking the box "Package deskew with board layout" Quartus takes care about package skews internally. Are the package skew differences deskewed using the same FPGA resouces as calibration shift ? >> If you do not enable the package deskew option, the Quartus Prime software will adjust the skews on the appropriate signals using the package delay numbers and we don't need to adjust for the delays with board traces. If you do enable the package deskew option, the Quartus Prime software does not use the package delay numbers for timing analysis, and you must deskew the package delays with the board traces for the appropriate signals for your design. If you want calibration to handle this instead of adjusting your board design, turn the deskew options off. However, Intel recommended to perform package deskew if your operating frequency is equal to 933Mhz and above using DDR4. For more details, you can refer to section 6.4.5 (page 253) in the user guide below. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf I sincerely hope this helps. Thanks Regards, NAli1
  • IHohm's avatar
    IHohm
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    7 years ago

    Hi NAli,

    thanks for your detailed answer, I just haven't recognized the section 2.8.6 in emi_plan.pdf.

    I checked board deskew just in ug_emif.pdf , sorry.

    I am wondering if this would work, too:

    1) Fit the design for device A with board deskew ticked. Adjust the trace length on PCB.

    2) Generate a report for the package skew differnces between device A and device B.

    3) Apply sdc timing constraints set_output_delay() for device B using the delay differences between the packages.

    This should replace the step

    "6. Calculate board skew parameters, only taking into account the board traces for device B, and enter that value into the parameter editor for device B."

    4) Fit device B with board deskew ticked.

    Regards

    IHohm

  • NurAida_A_Intel's avatar
    NurAida_A_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago
    Hi IHohm, Yes you can try. Just make sure you follow all the requirements needed for your IP and board design and ensure that the Report DDR timing report meet your timing requirement for both devices. Thanks Regards, NAli1