Arria10 DDR4 interface deskew limits

Hi NAli,

thanks for your detailed answer, I just haven't recognized the section 2.8.6 in emi_plan.pdf.

I checked board deskew just in ug_emif.pdf , sorry.

I am wondering if this would work, too:

1) Fit the design for device A with board deskew ticked. Adjust the trace length on PCB.

2) Generate a report for the package skew differnces between device A and device B.

3) Apply sdc timing constraints set_output_delay() for device B using the delay differences between the packages.

This should replace the step

"6. Calculate board skew parameters, only taking into account the board traces for device B, and enter that value into the parameter editor for device B."

4) Fit device B with board deskew ticked.

Regards

IHohm