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JOter's avatar
JOter
Icon for New Contributor rankNew Contributor
7 years ago

Arria V-Quartus 18/18.1 time quest constrains.

I have problems, with a Arria V-Quartus 18/18.1 and time quest constraints. It seems quartus does not apply the constraints file. The same Project Works properly with a cyclone III and Q13.1.

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  • JOter's avatar
    JOter
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hi,

    I send you both projects, so you can obtain all information.

    Regards

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    Can you check if the constraints are being ignored under 'Ignored Constraints'? Can you provide the timing report for both design?

    Thanks.

    • JOter's avatar
      JOter
      Icon for New Contributor rankNew Contributor
      7 years ago

      There are not errors. The problema is that the signal are delayed as spected.

      The signal re: RAM_CLK (CLK) and OUTPUT 0 (counter)

      We tested both signal in one scope, and we didn't notice any change between them changing the OUTPUT_DELAY constraints.

      Remenber we checked it also using a C III, and in this case we got the spected signal.

      We used the next constrains commands:

      set_output_delay -clock vt_RAM_CLK -max [expr $RAM_tsetup + $RAM_BDb_max - $RAM_CLK_DLY_MIN] [get_ports {OUTPUT[0]}]

      set_output_delay -clock vt_RAM_CLK -min [expr -$RAM_thold + $RAM_BDb_min - $RAM_CLK_DLY_MAX] [get_ports {OUTPUT[0]}]

      And

      set_output_delay -clock RAM_CLK -max [expr $RAM_tsetup + $RAM_BDb_max - $RAM_CLK_DLY_MIN] [get_ports {OUTPUT[0]}]

      set_output_delay -clock RAM_CLK -min [expr -$RAM_thold + $RAM_BDb_min - $RAM_CLK_DLY_MAX] [get_ports {OUTPUT[0]}]

      Best regards