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Hello,
I just wanted to check if there are likely to be any problems interfacing the following clock fanout (
http://www.ti.com/lit/ds/symlink/sn65lvds104.pdf ) which is 3.3v with 2.5v IO on the arria V. The differential specifications seem fine. My concern is with the "Fail Safe" 300k pull-ups on the Receiver. that will pull the lines high when not driven. Although this doesn't exceed the absolute maximum io voltage of 3.6 in the device datasheet, it is outside the common mode value specified for 2.5VLVDS on the device. When enabling the LVDS driver on the Arria V, the lines will briefly be at 3.3 volts. Could this be a problem?
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You can refer to the following KDB solution for further details:
https://www.altera.com/support/support-resources/knowledge-base/solutions/rd01242007_248.html https://www.altera.com/support/support-resources/knowledge-base/solutions/rd04282010_33.html
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