New ContributorArria V GX configuation issues
Hello, was hoping for some help with some configuration problems we've been having.
Our design (5AGXMB3G4) has a Nios II with an EPCS controller (altera_avalon_epcs_flash_controller) to interface to our configuration device (MT25QL256, using AS x1). Using quartus standard 18.1.1
We have noticed that the configuration in flash becomes corrupted over time. If we "examine" the flash with the quartus programmer, and compare the resulting jic file against the original jic used to program the flash, we generally see that the differences are very sparse, usually a few groups of four bytes set to zero near the start of the image. I've attached a screenshot where the diffs are highlighted (this is all the diffs in the entire 256Mb file).
We haven't found any hardware explanation for the corruption (supply rails all look good, sequenced properly, logic levels and pullup resistors are ok). The current theory is that the Nios is accidentally writing the flash due to some code bug (bad pointer, stack overflow, who knows). While we look for the true root cause, I wanted to also provide some protection against this accidental corruption by disabling writes to the flash outside of normal configuration operations.
We've considered using the API alt_lock_flash() to lock all sectors (bits 6,4:2 of the status register), but this operation is non-volatile and opens up some scenarios where doing remote updates might become impossible. Instead I'd like to make use of the Write Enable Latch (bit 1 of the status register).
To start with we wanted to just read the flash chip's status register so we can verify we are affecting it correctly. But we can't even get this to work. There doesn't seem to be an API for interacting with the status regsiter, but there are useful-looking macros like this:
status = IORD_ALTERA_EPCQ_CONTROLLER_STATUS(epcq_flash_info->csr_base)
But trying this yields status=0x20, which does not make sense. What are we doing wrong?
Regards,
Mike
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