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Altera_Forum's avatar
Altera_Forum
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11 years ago

Arria II reprograms itself from configuration ROM after it warms up

The problem is that I am using an Aria II which is being programmed by a configuration EPROM. The initial load is successful, and the board functions as expected. As the FPGA warms, the device seems to go into a mode of perpetually trying to reconfigure itself. The CONFIG DONE signal remains HIGH, but I can see NSTATUS toggle as DATA and DCLK lines go active. When the FPGA gets in this state, it seems to continuously try to reprogram itself. I can use spray-on coolant and get the FPGA to stay programmed, but it will just warm up again and go back into the same configuration cycle. The thing is the FPGA does not get warm at all (it starts reprogramming itself at ~87 degrees F). I though maybe there was a floating input that was drifting high or low as the board heated, but I have gone through all of the configuration signals and cannot see anything that is not tied one way or the other (pulled up or down). I have three boards that are doing this. Each board takes a different amount of time to reach the state, and I had to put one board in a heat chamber to see the failure. The current does not change more than 20mA from programmed state to the program recycle state. I am not sure I understand the mechanism that causes the Aria II to think it needs reconfiguring (e.g. CONFIG DONE never goes LOW). Also, Iw as wondering if I might have missed a configuration signal or something. Sny suggestions would be greatly appreciated.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    You need to look at everything that can cause the FPGA to go into configuration mode. One possibility is the internal power-on reset (POR) circuit. This circuit monitors several of the FPGA power rails. If any rail drops drops below a fixed threshold the POR circuit will be triggered and will put the FPGA back into the power-up reset state. If that power rail then recovers the internal reset will be released and configuration will commence, just like what happens on power-up. That would be my best guess as to what's going on. Read the Arria II documentation to see exactly what power rails are monitored and what the thresholds are. If you rule this one out then look at the other possibilities. There aren't that many.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thank you both for the replies. Actually, I have been looking into both of these. We had our manufacturer re-ball and reflow the FPGA, and I am awaiting return of the boards. I also looked at the power supply issue, and I somewhat suspect the 0.9V power supply. I used the same design that was used on the Aria II development board, and that design includes the use of a switcher (TPS40140 with two MOSFETs (CSD16411)) to generate the 0.9V. Still, I see some significant switching noise that I am having trouble filtering.