Arria II. Load Image issues. nstatus line toggling (?)

Hello.

I am trying to configure the Arria II GX through FPP. All MSEL lines are low.

Here is the status of the different control pins during the process:

Power Supply reset:

nstatus: low | init_done: high | conf_done: low

nCONF toggled low then high:

nSTATUS toggles high/low/high, then:

nstatus:high | init_done: high | conf_done: low

transfering data:

before the 50,000th byte, status lines stay exactly as before.

between the 50,000th and 61,000th byte, this pattern will happen about half a dozen times:

init_done goes low for 20ms, then back high. on the rising edge of init_done, nstatus goes low for 65ms, then back high.

on the 61,300th byte transfered, the same pattern will happen, but nstatus will not go back high. it stays low and whatever I try to do, the FPGA stays stuck in that stage until I reset the power.

I do not manage to understand what is happenning here. my BIN file is 1Mbytes long, so this happens early in the transmission, but not as early as I would have expected for a data format issue.

extra information:

My DCLK is ~18ms, and 50% duty cycle. (I have tried with a slower clock, it didn't change anything)

I transmit the MSB on Data7 and LSB on Data 0

I hold the data during DCLK high, toggle it during DCLK low

I would appreciate any help or any direction to get help