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Honored ContributorArria II GX: Transceiver CMU PLL Reset
Hello,I have a problem with resetting my transceiver design.I'm testing on the Arria II GX Devkit and I'm using Quartus 9.1sp1.Sometimes after I pushed the reset button the transmitter sends wrong bits over the HSMC loopback header.In the tx reset controller the pll_powerdown is set for more than 1us as mentioned in the Device handbook on page 505.If the failure occured and I set the tx_digitalreset via an other button the problem stays.So I think there must be a problem with the CMU PLL, but the pll_locked signal stays high.I synchronize the inputs and added some debouncing for the push buttons.I verfied the data is correct that goes in the altgx component with Signaltap.I also looked with an oscilloscope on the serial data line. With the decoder in the oscilloscope the failure is visible. It cannot decode all characters.I could not see any abnormality in the eye diagram. But I'm not so familiar with the oscilloscope yet.Does anybody have an idea?Thank you!Kippis
3 Replies
Altera_ForumHi,
I have a question regarding the reset sequence. What do I have to send during the rx offset cancellation? Thank you, Kippis- Altera_Forum
Hi dhtang,
thank you for your answer! I checked this. In my design the reference clock pre devider is 1. I also checked the pll_locked signal. It goes low if I press the reset button. Kippis - Altera_Forum
Please check if the pll_locked signal de-assertion when you assert pll_powerdown? There is one issue on Arria II GX's pll_locked signal which is similar to Stratix IV device. Refer to Stratix IV errata for the workaround(www.altera.com/literature/es/es_stratixiv_gx.pdf )
