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Thorsten_S's avatar
Thorsten_S
Icon for New Contributor rankNew Contributor
5 years ago

Arria 10 transceiver PLL spacing

UG-01143, section 3.1.1 states several spacing constraints on ATX and fPLLs which operate at the same VCO frequency. What happens when these constraints are violated (apart from Quartus issuing a c...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


I don't have the full detail but we have seen issue in the past that noise coupling effect may occurs that caused increased jitter in neighboring transceiver channel when PLL spacing requirement is violated.


There is no good way to quantify the coupling effect hence came the design guideline to follow the PLL spacing requirement to avoid putting user design at risk.


Thanks.


Regards,

dlim