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PJoer2's avatar
PJoer2
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6 years ago

Arria 10 Transceiver clock inputs routed to I/O pll(s)

Hi, We would like to know whether it is possible to use a 20 Mhz HCSL clock connected to one of the ARRIA10 **transceiver clock inputs** as input to I/O plls (not fplls) inside the FPGA. Testing ...
PJoer2's avatar
PJoer2
Icon for New Contributor rankNew Contributor
6 years ago

Hi,

many thanks for the prompt answer.

For our reference, can you please point me to the datasheet/page where it is mentioned that

min XCVR refclk is 25 MHz?

For min fpll refclk, I can find 25 MHz in the ARRIA10 datasheet.

For XVCR refclk I can not find a specification...maybe I have tomatos on the eyes :).

Or if there was a statment about XCVR refclk necessarilly going through fpll to reach iopll, this would of course also be sufficient.

Many thanks again and kind regards

Philipp

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago
Hi, Sorry for any confusion. Yes, you are right. I am referring to TX PLL refclk frequencies ie ATX PLL, CMU PLL and fPLL in the Arria 10 datasheet. I believe it is the same table that you are referring to. The ATX, CMU and fPLL are sourcing their refclk from XCVR refclk pin. In other words, these frequencies are validated supported frequencies for XCVR refclk. Please let me know if there is any concern. Thank you. Best regards, Chee Pin