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PJoer2's avatar
PJoer2
Icon for New Contributor rankNew Contributor
6 years ago

Arria 10 Transceiver clock inputs routed to I/O pll(s)

Hi, We would like to know whether it is possible to use a 20 Mhz HCSL clock connected to one of the ARRIA10 **transceiver clock inputs** as input to I/O plls (not fplls) inside the FPGA. Testing ...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

As I understand it, you are trying to share and connect the XCVR refclk to an IO PLL and you understand that XCVR jitter performance will be impacted. For your information, as per the device datasheet, the minimum frequency validated for XCVR refclk is 25MHz which is for fPLL. Currently, there is no data for supported refclk freqeuncy at 20MHz. Thus, it is difficult to guarantee the functionality of XCVR refclk with 20MHz. You might need to look into using support frequency range. Sorry for the inconvenience.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin