Arria 10 Transceiver clock inputs routed to I/O pll(s)

Hi,

We would like to know whether it is possible to use a 20 Mhz HCSL clock connected to one of the ARRIA10 **transceiver clock inputs**

as input to I/O plls (not fplls) inside the FPGA.

Testing this with a Quartus design does not show any errors. Within the post-mapping technology map viewer things also look reasonable.

However, what still brings us to ask this question are the following two points:

1)Within timing analysis of the clock path we encounter a signal like the following<input_clk_name>/ch1_pld_pma_fpll_fbclkout_lc_lvpecl_to_coreclk

Since fpll is mentioned we are afraid that the clock passes an fpll which accepts only input frequencies **above 25/30 MHz** and would fail for our 20 MHz clock signal

2)Within ARRIA10 datasheets and reference guides we can not find a clear statement which says something like "a transceiver clock input signal can be routed to the global clock network (and hence to an I/O pll) without having to pass the fpll.

Note: We know that using a dedicated clock input (not transceiver clock input) would solve the problem. However, for our specific application we have other reasons to use the transceiver clock input instead. In addition we are aware that if the above is possible, jitter would be worse.