Arria 10 (speed grade 3) has worse timing performance than Cyclone 10 GX (speed grade 5)
I am porting a design from a 10CX085YF67215G (Cyclone 10 GX, speed grade 5) to a 10AX022C4U19E3LG (Arria 10, speed grade 3). I am using Quartus Prime Pro Edition 21.3.
The design meets timing in th...
As confirmed by @RichardTanSY_Altera , this is expected behavior. Although it is totally baffling that a more expensive device family, combined with a superior speed grade leads to worse timing performance, I am satisfied that my question has been answered.
I am sorry to hear that you have a bad experience with the other forum posts in the past but what I can do for you is to provide the support needed in this case.
Thus, we can't make these comparison apple-to-apple between Arria 10 and Cyclone 10 GX device, and it is also not compatible with speed grade 3 and speed grade 5.
The speed grade 3 of A10 is not the same as speed grade 5 of C10 so it will impact the timing.
The reason I request the design is so that we could check for anything other that the difference in device speed grade.
It is alright if it is not convenience to share your design with us. Perhaps you could provide some insight on below inquiries?
1. Previously you mentioned that in the Arria 10 device, the pins with the timing failures are mapped to I/O bank 2A, which is an LVDS I/O bank.:
May I know the reason you use bank2A instead of other bank?
2. Beside PHYlite IP, does the design contain other IP? How much is the logic utilization of the design?
3. Do you has any SDC file to constrain the timing? Since you are not using dynamic reconfiguration, there will another way to constraint.
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