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hcom's avatar
hcom
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Arria 10 (speed grade 3) has worse timing performance than Cyclone 10 GX (speed grade 5)

I am porting a design from a 10CX085YF67215G (Cyclone 10 GX, speed grade 5) to a 10AX022C4U19E3LG (Arria 10, speed grade 3). I am using Quartus Prime Pro Edition 21.3. The design meets timing in th...
  • hcom's avatar
    hcom
    3 years ago

    As confirmed by @RichardTanSY_Altera , this is expected behavior. Although it is totally baffling that a more expensive device family, combined with a superior speed grade leads to worse timing performance, I am satisfied that my question has been answered.

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

I will need to consult our internal team in regards to this IP, could you help to clarify below inquiries:

1. What is the interface frequency of the design?

2. Do you use dynamic reconfiguration in their design?

3. The timing failure is happened in output pins but which is the timing failure path the between IO to FPGA core or external to IO?



hcom's avatar
hcom
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

@RichardTanSY_Altera Thank you for your help.

  1. I need to support a range of frequencies (set at compile time in different FPGA builds), up to 300 MHz. But this is a source-synchronous interface, so the more pressing issue is to meet the setup and hold requirements of the external device.
  2. No, I do not want to use dynamic reconfiguration.
  3. The Arria 10 (speed grade 3) appears to be consistently slower than the Cyclone 10 GX (speed grade 5), so timing failures can happen anywhere.