Arria 10 SoC FPGA power fail safe update from HPS in Linux (no access to u-boot)

Hi,

By default a peripheral and core image is stored in the external persistent storage which is flashed by u-boot. To update, u-boot can fetch new images over tftp or Linux can overwrite these images and perform a reboot. First is not feasible in our setup at the user, and the latter is not power fail safe.

Solution idea #1:

It would be sufficient to flash a fixed minimal peripheral image by u-boot to initialize the DDR controller only to let Linux boot. Then the FPGA can be fully configured from Linux with an image stored in the file system which the user can change.

Question #1: Can a combined image be written to the FPGA without resetting the DDR controller as Linux needs it to operate? Combined because peripherals can change, only DDR remains.

Question #2: Can partial reconfiguration work from early IO release mode or only if the FPGA entered user mode? Reference Manual a10_5v4 chapter A.8.2 says only in user mode.

Solution idea #2:

If non of the above can work, then two peripheral images can be stored. One user and one back up (only to initialize DDR controller). If user one is corrupted or unable to flash, then u-boot can fall back to the back up one, let Linux start so it can re-write the user one again and reboot. (If core needs to be re-written can be checked by an application, the critical is the peripheral.)

Question #3: Is there a driver ready to use to address write in flash outside the file system in https://github.com/altera-opensource/linux-socfpga/tree/socfpga-4.9.78-ltsi

Question in general: What is the most efficient (uses least space) way of handling such an FPGA update?

Thanks for the replies in advance!

Regards,

Tibor