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TSege1's avatar
TSege1
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5 years ago

Arria 10 SoC EMIF Input clock jitter requirment

I am designing a new board with Arria 10 SOC. This FPGA is connected on board to two DDR4 16Bit components. I found in Intel UG-20115 doc "External Memory Interfaces Intel Arria 10 FPGA IP User Gui...
TSege1's avatar
TSege1
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5 years ago

Thank you for your reply

I know the jitter performance of my reference clock. I have a datasheet for it that states it clearly.

I am trying to understand what the requirements are to make sure that my reference clock is adequate.

Could you explain what are the jitter requirements for the reference clock? Where do these requirements come from? Are they written in some spec.?

Are the jitter requirements dependent on DDR4 data rate?

Regards,

yoichiK_altera's avatar
yoichiK_altera
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5 years ago

Hi

Jitter amount affects the timing margin in the IP. If the reference clock has more jitter than requirement there may be malfunction on the IP due to the timing issue. The jitter requirement is consistent regardless any DDR4 data rate.