Arria 10 SGMII CDR does not lock to data

I see that you have a question regarding termination for the dedicated GXB reference clock.

The GXB reference clock do indeed provide internal differential terminations and should be AC coupled.

The only IO standard that should be DC-coupled with external terminations is HCSL (HCSL standard is used for PCIE interface).

The proper .qsf assignment to define the clock termination is "XCVR_A10_REFCLK_TERM_TRISTATE" and is shown in Section 8.9.1 of the A10 Transceiver PHY User Guide:

https://www.intel.com/content/www/us/en/docs/programmable/683617/

Example syntax:

set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to <dedicated refclk pin name>

rx_is_lockedtodata status output port indicates that the RX CDR is currently in lock to data mode or is attempting to lock to the incoming data stream.