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FabianL's avatar
FabianL
Icon for Occasional Contributor rankOccasional Contributor
10 months ago

Arria 10: Remote Update may brick FPGA and Factory Fallback won't work

Hello, we have observed some critical failures when doing tests with various potential error scenarios concerning a remote Update of the FPGA bitstream in the attached SPI Flash device. We could re...
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Farabi's avatar
Farabi
Icon for Regular Contributor rankRegular Contributor
4 months ago

Hello,


Thanks for your update. I am not sure what happened to your design, but few things to check below:


1- Can you make sure : RU_WATCHDOG_ENABLE = 1 is written before triggering reconfiguration, and make sure the setting is persist during configuration. Some reconfig reset settings.


2- Please make sure the watchdog timeout not too. eg. Dont set RU_WATCHDOG_TIMEOUT = 0xFFF (this is too long)


3- Please confirm the application image does not contain any logic that somehow triggers/modify RU_RESET_TIMER register.


regards,

Farabi


FabianL's avatar
FabianL
Icon for Occasional Contributor rankOccasional Contributor
4 months ago

Hello Farabi,

  1. Yes I have double checked the RU_WATCHDOG_ENABLE = 1 is set before reconfiguration. This was also proved by the test with the misaligned bitstream image. Without the watchdog enabled, the misalinged image reconfiguration gets stuck, with the watchdog enabled it works as expected and triggers a factory fallback.
  2. Why is this too long? I have actually set the watchdog timeout to 0xFFF.
    1. But it works in case of misaligned application loads, so why should this a problem in normal operation?
    2. What is the unit of the watchdog timeout register? is it clock cycles? if yes which clock cycles?
  3. The application image is not setting any registers in the Remote Update Intel FPGA IP Core. It only reads RU_RECONFIG_TRIGGER_CONDITIONS (register 0)

best regards

Fabian