Forum Discussion
Hello Fabian,
Sorry to keep you waiting. Few steps to check for debug:
Could you please check below?
1- confirm factory image is correctly programmed at boot address.
2- ensure application image is programmed at known valid address.
3- verify the .jic file start address matches the RU_PAGE_SELECT value.
Application Image validation.
1- Confirm application image can be loaded successfully when normal condition
2- Confirm FPGA able to enter user mode (CONF_DONE-> HIGH)
3- Confirm watchdog is not enabled - no writes to RU_RESET_TIMER
Factory Image validation.
1- Power up and confirm it boot into factory image.
2- read RU_RECONFIG_TRIGGER_CONDITIONS to confirm power up state (Bit0 = 0)
3- Factory image set to below parameters:
a. RU_PAGE_SELECT = application image address
b. RU_CONFIGURATION_MODE = 1 (Application Mode)
c. RU_WATCHDOG_TIMEOUT = set the correct value
d. RU_WATCHDOC_ENABLE = 1
4- trigger reconfiguration by writing 1 to RU_RECONFIG
Test fallback mechanism.
1-Manually corrupt the application image (erase some part or misalign)
2- Check if FPGA fail to enter user mode
3- check if FPGA fallback to factory image
4- read the RU_RECONFIG_TRIGGER_CONDITIONS reflecting the correct cause(Bit1 = watchdog timeout)
If you have followed all above and still you observed the fallback mechanism doesn't kick in. We will need your design for escalation.
regards,
Farabi