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CHatz's avatar
CHatz
Icon for New Contributor rankNew Contributor
3 years ago

Arria 10 PTP Implementation using Triple Speed Ethernet IP Core.

Our board is based on the Arria 10 FPGA. We are using the KSZ 9031 PHY. We would like to implement PTP (Precision Time Protocol) on the board. Would the IP Core interface with the KSZ9031 PHY in ...
ZiYing_Intel's avatar
ZiYing_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi Costas,

I would like to suggest you to use the Intel IP as to implement your design as we do have the example design of IP which can let you refer to do some changes according to your desire design.

If you are using external PHY for the triple speed ethernet with RGMII mode, you may refer to link below Section 5.3.1, pg 104, https://www.intel.com/content/www/us/en/docs/programmable/683402/22-1-20-0-0/system-with-mii-gmii-or-rgmii.html

We suggested you to do the changes as the user guide stated so that to prevent any error occur.

Best regards,

Zi Ying