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GDeXi's avatar
GDeXi
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Arria 10 Native Transceiver Phy

Hi I got same question like he, Can you give me some answers? https://forums.intel.com/s/question/0D50P00003yyH7FSAU/arria-10-native-transceiver-phy-10gbaser?language=en_US&t=15...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Sorry for any confusion. I would like to further elaborate on the right clock frequencies for the 10GBaseR application. The tx/rx_corelkin frequency should be 156.25MHz for XGMII. Whereas the tx/rx_clkout would be data rate/PCS-PMA interface which is 257.8125MHz. Note that tx/rx_clkout are not directly connected to tx/rx_coreclkin. The current Figure 55 seems to be confusing. I will feedback to Factory on the confusion and will request them to update the Figure to reflect the correct connection. Sorry for the inconvenience.

PPerd2's avatar
PPerd2
Icon for New Contributor rankNew Contributor
5 years ago

Will PHY work stably if I clock (in 10gbase-r configuration) tx/rxcoreclkin port with:

1. tx_pma_div_clkout with division factor 33?

2. generated clk 156.25 MHz by IOPLL?

3. generated clk 156.25 MHz by IOPLL with reference like Native PHY?