Forum Discussion
Occasional ContributorArria 10 Native Transceiver Phy
Regular ContributorHi,
Sorry for any confusion. I would like to further elaborate on the right clock frequencies for the 10GBaseR application. The tx/rx_corelkin frequency should be 156.25MHz for XGMII. Whereas the tx/rx_clkout would be data rate/PCS-PMA interface which is 257.8125MHz. Note that tx/rx_clkout are not directly connected to tx/rx_coreclkin. The current Figure 55 seems to be confusing. I will feedback to Factory on the confusion and will request them to update the Figure to reflect the correct connection. Sorry for the inconvenience.
GDeXiThe tx/rx_corelkin frequency should be 156.25Mhz for XGMII. Whereas the tx/rx_clkout would be data rate/PCS-PMA interface which is 257.8125Mhz. OK,This is very reasonable. Could you tell me how frequencies about fifo write and read interface ? it is 156.25Mhz ? if yes, How do 156.25 Mhz and 257.8125Mhz cross clock regions?
PPerd2New Contributor
Will PHY work stably if I clock (in 10gbase-r configuration) tx/rxcoreclkin port with:
1. tx_pma_div_clkout with division factor 33?
2. generated clk 156.25 MHz by IOPLL?
3. generated clk 156.25 MHz by IOPLL with reference like Native PHY?
