Arria 10 Native Transceiver PHY - 10GBASE-R

Sorry I can't answer any of your questions specifically, but know that I opened a service request with Altera a few weeks ago regarding 5.2.2.10.5 and the gentleman from Applications Engineering agreed that it was a typo and he submitted a request to have it corrected. From what I've read, I doubt that is the only typo. The Applications Engineer said they would publish a KDB solution--whatever that is.

Also, the Applications Engineer recommended I refer to Figure 127 for information on when to assert the read signal (figure 126 is for the write side), but I find both of those diagrams questionable. They both recommend asserting the read/write signal *asynchronously* driven by the pempty/pfull signal--which seems a little odd. Furthermore, the data signals in those two diagrams doesn't seem to be lined up correctly.