iiwan
New Contributor
New ContributorArria 10 Native Phy Settings
I am new to Arria 10. When I configured TX PMA, did not find TX PLL clock frequently to choose, as It was in Stratix V. So Arria 10
uses RxRefClk for TX PLL? Or how have I to configure? My clk is same for tx and rx.
And second question, in Stratix V I used 8b/10b codec, word aligner and byte ser/des x2, and had to use byte ordering. So in Arria 10 I did not find byte ordering settings neither in platform designer nor in documentation. I have to implement it by myself, or this functionality inserted in word aligner?
uses RxRefClk for TX PLL? Or how have I to configure? My clk is same for tx and rx.
And second question, in Stratix V I used 8b/10b codec, word aligner and byte ser/des x2, and had to use byte ordering. So in Arria 10 I did not find byte ordering settings neither in platform designer nor in documentation. I have to implement it by myself, or this functionality inserted in word aligner?
Hi,
As I understand it, you have some inquiries related to A10 XCVR instantiation. Please see my responses as following:
1. In Arria 10, the TX PLL ie ATX PLL is instantiated separately and connect to Native PHY
2. User would need to build own byte ordering block in core logic. Sorry for the inconvenience.
Please let me know if there is any concern. Thank you.
