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Altera_Forum's avatar
Altera_Forum
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8 years ago

Arria 10 multiplier speed

I'm rather new to practical FPGA design though I have a lot of theoretical background. I'm working with (starting/trying to would be more accurate) the Arria 10 development kit which has Arr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

The datasheet figures are always the theoretical maximum of the silicon internal to the DSP. What will kill the timing is getting data in and out of the DSP.

Always take the datasheet max with a pinch of salt, and so I only expect 75% in a user design with extreme pipelining and timing control. 50% is an easier to achieve figure.