Arria 10 M20k block usage- More block with less memory bits?

I remain very unsatisfied with the proposed possibilities. The most recent ( Best Fit vs Safe Fit) cannot be confirmed or checked. I also don't even have a definition for the two options.

Either way it does nothing to explain why the Quartus compilation claims that the design needs MORE memory bits on the small chip than on the larger (see my first post). If we had a situation where the smaller chip did not fit but the number of memory bits required was consistent then I could understand why it wasn't working. But that is not the case.