Occasional Contributor
Super ContributorUnderstood, let me know the feedback by end of the week.
Occasional ContributorHere are my findings so far-
1- I implemented a version of the design with reduced memory just to see when it would start fitting. I discovered that when I reduce memory usage in order to fit onto the smaller chip then Quartus uses MLABS. However when I try to implement the full design and fitment fails. The report then shows 0 MLAB usage.
So it is tricky to say what the problem is for the failing design.
For the large Arria - It shows 2415 MLABS used.
For the Small Arria with reduced memory - it shows 3653
For the full design on smaller Arria- is shows 0
Interestingly it states that MLABs can be up to 1/2 of total LABs. But in neither case does it use half.
And for the Small Chip design w/ reduced memory it only uses 92% of Logic and MLABs
2- ALM usage of the Full design on smaller chip, which fails fitment is 119,902 (48%)
ALM usage is 185,619 on the small chip (74%) w/ reduced memory
ALM usage is 172,802 on the large chip (40%)
3- I could not see any differences in port depth.
I have not yet tried forcing an instance into an MLAB. It is failing by such a large degree I'm not sure which instances to try or how many.
4 I am not able to determine whether this applies or not. Since the design fails fitment it can't run timing analysis
This all brings me back to my initial question.
Why does the smaller chip claim to need 36,086,072 memory bits and 3,055 blocks , when the larger chip only needs 35,349,568 bits and 2713 blocks?
Also please note that 36,086,072 bits is only 83% of the smaller Arria chip and should fit (in my experience).
Thanks again.
Occasional ContributorAdditional information-
I attempted to force several memory instances to MLAB via
set_instance_assignment -name RAM_BLOCK_TYPE MLAB -to <ram_instance>
This had no effect.
However, what did work was altering fifos in the platform designer.
I discovered that Quartus was constraining all fifos to use only M20k.
This seemed odd to me, so I looked at them in the platform designer. They were all set to 'Auto' under the "What should the memory block type be?". To test this out I set some of them to MLAB. Then I saw a significant reduction in M20K use and MLABs were selected instead.
It seems that for some reason Quartus is interpreting 'Auto' to be constraining to M20k only? Not sure how else to explain it.
These fifos are all set to 'Auto' in the successful project on the larger chip and Quartus does not constrain them to M20k there. But on this smaller chip it does.
