Arria 10 M20k block usage- More block with less memory bits?

Sorry for the late reply as I am off for a week

The fact that the smaller Arria 10 design isn't using any MLABs while the original one does is likely the root cause of the extra M20K block usage. MLABs (which use ALM-based memory) help offload some RAM demand from M20Ks, so their absence forces Quartus to place everything in M20Ks, explaining the increased block count.

Possible Reasons MLABs Are Not Being Used

Even though the MLAB-related settings match between projects, there are a few other factors that might be preventing Quartus from using MLABs in the smaller device:

1. MLAB Utilization Can Depend on Fitter Heuristics

Even if "Auto RAM to MLAB Conversion" is ON, Quartus still makes a decision based on available resources and timing feasibility.

Since the smaller device has fewer ALMs and M20Ks, Quartus may have chosen to disable MLAB usage to meet timing or placement constraints.

Check in the Fitter Report

Look at the MLAB Utilization section in .fit.rpt in both projects and see if Quartus states a reason for not using MLABs.

Quartus may be rejecting MLABs due to high logic utilization or routing congestion in the smaller chip.

2. Synthesis and Fitting Differences Due to Chip Resource Constraints

Since the smaller FPGA has fewer total ALMs, Quartus might prioritize ALMs for logic instead of MLABs for memory.

If the larger FPGA had excess ALMs, Quartus may have felt comfortable assigning MLABs, but in the smaller FPGA, it might reserve ALMs for combinational logic instead.

Check Logic Utilization

Open Fitter → Resource Usage Report and see if ALM usage is significantly higher in the smaller device compared to the original.

If ALM utilization is high, Quartus might be avoiding MLABs to prevent routing congestion.

3. Memory Depth and Width Constraints for MLAB Usage

MLABs can only store 32-bit wide words with a depth of 640 words. If Quartus synthesized the RAM slightly differently (e.g., with increased depth/width due to address alignment constraints), it may have disqualified MLAB usage.

Check RAM Depth & Width

Look at the RAM Summary Report (.ram_summary.rpt) and check if:

Quartus changed the width or depth of certain RAM blocks.

Some RAMs that previously fit in MLABs are now too deep or too wide.

Manually force certain RAMs to use MLABs and see if Quartus accepts it

set_instance_assignment -name RAM_BLOCK_TYPE MLAB -to <ram_instance>

4. MLAB Timing Constraints Might Be More Strict in the Smaller FPGA

MLABs have higher access latency than M20Ks. If Quartus detected that using MLABs would violate timing constraints (especially due to tighter placement in the smaller FPGA), it may have disabled their use.

Check Timing Report

Run a Timing Analysis (.sta.rpt) and check for MLAB-related timing violations.

If Quartus is failing to meet setup/hold timing with MLABs, it may have automatically forced all RAMs into M20Ks instead.