Arria 10 HSSI receiver PHY CDR reference clock related questions

The Arria 10 Device Datasheet / Arria 10 Native PHY Datasheet are not very clear on the HSSI RX reference clock requirements. It would help us greatly if you could answer the following HSSI reference clock related questions.

Could you please specify what is the minimum valid RX HSSI reference clock frequency for Arria 10?

The A10 Native PHY GUI limits RX CDR refclock frequencies to above 50 MHz. Could you please confirm that this is indeed the minimum value? A10 datasheet does not list the value, there is however a minimum input reference clock frequency of 25 MHz for fPLL and HDMI protocol, but no minimum value for CDR. Why is fPLL minimum frequency relaxed for HDMI protocol and not for others? Is the 50 MHz an arbitrary value?

With our design, where we receive HDMI and use the input TMDS clock directly, we are able to lock on almost all formats with pixel clocks between 25 and 50 MHz, but some do not work. We are investigating whether we are out of limits for the CDR refclock or there is some other issue. We are not using the Intel HDMI refdesign with the additional clock doubling IOPLL.

What are the jitter requirements for the RX CDR clock? Is it as sensitive as TX PHY reference clock? If we use a low quality CDR refclock, will this affect our RX BER or PHY lock to data behavior?

Is it possible to somehow reconfigure the HSSI CDR circuitry to support refclock below 50 MHz? What would be a suitable document on this topic?

Thank you for Your help