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Rob49's avatar
Rob49
Icon for New Contributor rankNew Contributor
3 years ago

Arria 10 HPS EMIF DDR4 16-bits "Fitter was unable to place an EMIF/PHYLite system"

Hi. I'm working on a custom board using a Soc FPGA Arria 10 (10AS048E4F29E3SG) with DDR4 memory (using two components MT40A512M16(TB)062E) linked to the HPS module. Because of a yet unexplained e...
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Rob


In the case for the HPS EMIF. In normal use case, the HPS IP core and HPS EMIF IP are usually connected together automatically and we do not need to implement additional constraints.


If we were to make changes to the pin out there are some conditions that to be followed.

Refer to section 3.7.1 in the document below:

https://www.intel.com/programmable/technical-pdfs/683106.pdf



Regards

Jingyang, Teh