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TRock
New Contributor
New ContributorArria 10 GX Transceiver Dynamic Recalibration
Hi, My design's master clock is phase-locked to an external reference tone. The reference clock may be disconnected then reconnected. It's always approximately the same frequency, while the phase of...
TRockNew Contributor
New ContributorIt looks like the answer is to instantiate the PHY modules (PLL, rst ctrller, and PHY) inside Qsys as Nios MM slaves. Write to address 0x100 of the high-speed PLLs to initiate calibration. I hope ...
