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Altera_Forum's avatar
Altera_Forum
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9 years ago

Arria 10 GX pcie and xaui transceiver interaction

Hello, I am seeing something that I cannot understand from the transceiver user guide. Arria 10GX with 12 tranceiver channels. Of the 12 XCVR channels, I have one x4 PCIe Gen 3 HARD IP and 4 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Also, does CLKUSR play a part in this? I have the CLKUSR at 100MHz coming into the device. So I am not sure why PCIe should get in the way of XAUI lanes. PCIe has its own reference clock and XAUI interface it's own. What's interesting is that my colleague here has the exact same issue with the PCIe and JESD204B. It seems like there is something in the PCIe core that we do not understand.