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TWatt3's avatar
TWatt3
Icon for New Contributor rankNew Contributor
4 years ago

Arria 10 GX FPGA with PCIe core no coreclkout_hip

Hello, I have a board with an Arria 10 GX FPGA on it. We are using the PCIe core in the FPGA. Using SignalTap, we are able to see the PCIe refclk toggle at the expected rate (100 MHz). W...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Could you share the signal tap for the below signals? Besides this, could you try running the example design?


serdes_pll_locked

coreclkout_hip

refclk pin

pll_cal_busy

tx_cal_busy

rx_cal_busy

pin_perst

npor

reset_status

pll_locked

rx_is_lockedtoref

rx_is_lockedtodata

ltssmstate[4:0]

lane_act[3:0]


Thanks

Best regards,

KhaiY


Lilian_61's avatar
Lilian_61
Icon for New Contributor rankNew Contributor
3 years ago

Hi KhaiY,

I want to monitor these signals, but I don't know how to connect then on SignalTap.

I didn't find these output of Hard IP.

Are they the internal signals? How can i connect them correctly and quick to SignalTap.

Could you give some instruction on this?

Thanks

Lilian_61