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TWatt3's avatar
TWatt3
Icon for New Contributor rankNew Contributor
5 years ago

Arria 10 GX FPGA with PCIe core no coreclkout_hip

Hello, I have a board with an Arria 10 GX FPGA on it. We are using the PCIe core in the FPGA. Using SignalTap, we are able to see the PCIe refclk toggle at the expected rate (100 MHz). W...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI,


The CLKUSR pin clocks the calibration engine. All transceiver reference clocks and the CLKUSR clock must be free running and stable at the start of FPGA configuration to successfully complete the calibration process and for optimal transceiver performance.


Thanks

Best regards,

KhaiY