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TWatt3's avatar
TWatt3
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4 years ago

Arria 10 GX FPGA with PCIe core no coreclkout_hip

Hello, I have a board with an Arria 10 GX FPGA on it. We are using the PCIe core in the FPGA. Using SignalTap, we are able to see the PCIe refclk toggle at the expected rate (100 MHz). W...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


It looks like the PLL, TX and RX calibration are still in progress. Is the CLKUSR pin clocked from an external free-running clock source and it is available during device power-on?


Thanks

Best regards,

KhaiY


TWatt3's avatar
TWatt3
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4 years ago

Hi KhaiY,

I have the CLKUSR pin tied to ground. I checked the "Intel Arria 10 GX, GT and SX Device Family Pin Connection Guidlines" document (pcg-01017.pdf and see that the CLKUSR pin must be connected to a clock for the transceivers to work.

So this is probably the problem?

Thanks.

Todd

  • TWatt3's avatar
    TWatt3
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    4 years ago

    Hi KhaiY,

    Is the only option for the CLKUSR clock to drive the CLKUSR pin from an external oscillator for the transceivers?

    Is it possible to assign CLKUSR within the FPGA from a 100 MHz clock and not use the external pin?

    Thanks.

    Todd