Forum Discussion
MehmetFide
New Contributor
New ContributorArria 10 GX: 64 bit atomic access to Avalon Bus through PCIe?
Hi,
We have an external processor Arm Cortex A53 with Linux 5.4 aarch64 connected to an Altera Arria 10 GX FPGA through a PCIe bus.
On the FPGA side, we have an Avalon bus, all addresses are se...
Wincent_Altera
Regular Contributor
Regular ContributorHi,
If you just want to use PCIe IP that interact with memory directly, then pls consider checking out below example design that use (PCIe) only, no DMA
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-a10-pcie-avmm.pdf
- This is the example design that you can generate from PCIe IP directly
- This example design currently connect to on chip RAM but you can replaced with DDR4 if you want
Regards,
Wei Chuan
