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MehmetFide's avatar
MehmetFide
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3 years ago

Arria 10 GX: 64 bit atomic access to Avalon Bus through PCIe?

Hi, We have an external processor Arm Cortex A53 with Linux 5.4 aarch64 connected to an Altera Arria 10 GX FPGA through a PCIe bus. On the FPGA side, we have an Avalon bus, all addresses are se...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel


  • MehmetFide's avatar
    MehmetFide
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi @Wincent_Altera,

    All BAR registers definition and implementations are inside the Quartus.

    When we try to access the memory area in FPGA from Linux, there are couple of options like Altera doing it here

    Those are

    ioread8 -> Works fine

    ioread16 -> Works fine

    ioread32 -> Works fine

    ioread64 -> Doesn't work and causes FPGA PCIe to be crashed

    Avalon DMA -> Works fine

    I'm trying to understand what is special with 64 bit direct access to make it non functional.

    Thank you.