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MehmetFide's avatar
MehmetFide
Icon for New Contributor rankNew Contributor
3 years ago

Arria 10 GX: 64 bit atomic access to Avalon Bus through PCIe?

Hi, We have an external processor Arm Cortex A53 with Linux 5.4 aarch64 connected to an Altera Arria 10 GX FPGA through a PCIe bus. On the FPGA side, we have an Avalon bus, all addresses are se...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


I am not familiar with the platform and code you are using.

Is that feature inside Quartus ? or it is from the driver ?


Why you need to change the IOread ?


Regards,

Wincent_Intel