Forum Discussion
AHX
New Contributor
1 year agoHi,
First of all: Thanks for your reply. I've changed our design and was able to synthesize it. Now we need to do some heavy hardware modification on our card to test this.
Follow up question: As already written we're facing this problem on a different FPGA (different bank layout).
Could you please tell me how to connect the clocks? I'm attaching our QSF file (renamed to rtf).
RongY_altera
Contributor
1 year agoSimilarly, your pcie_refclk for this should be either PIN_R24 or PIN_U24. Current location PIN_N24 is not recommended.
Regards,
Rong