Forum Discussion
Hi,
First of all: Thanks for your reply. I've changed our design and was able to synthesize it. Now we need to do some heavy hardware modification on our card to test this.
Follow up question: As already written we're facing this problem on a different FPGA (different bank layout).
Could you please tell me how to connect the clocks? I'm attaching our QSF file (renamed to rtf).
- RongY_altera1 year ago
Contributor
Similarly, your pcie_refclk for this should be either PIN_R24 or PIN_U24. Current location PIN_N24 is not recommended.
Regards,
Rong
- Mare11 months ago
New Contributor
Hi, Are there any restrictions when mixing two different interfaces on the same Transceiver bank? For instance PCIe and two SFPs. Suppose we take Bank 1C and 1D and put on it PCIe x4 which is split between both. Where should we put an additional two SFP interfaces (each SFP uses one RX and one Tx pair plus one dedicated clock input).