New Contributor
Regular ContributorHello,
Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 L-tile and H-tile device transceiver pins do not support ‘Hot-Socketing.’ Fully configure the transceiver block before driving or having any activity on the Intel Cyclone 10 GX and Intel Arria 10 device transceiver pins.
We would advise not to do that in unpowered state. The Arria® 10 device dedicated transceiver pins are not subject to the same hot-socketing limitations of the general purpose I/O pins. It is OK to drive the dedicated transceiver pins during power-up and power-down sequencing of Arria 10 devices.
Thank you.
Amin
ContributorHi Amin,
"The Arria® 10 device dedicated transceiver pins are not subject to the same hot-socketing limitations of the general purpose I/O pins. It is OK to drive the dedicated transceiver pins during power-up and power-down sequencing of Arria 10 devices."
Above statement is confusing with
"Fully configure the transceiver block before driving or having any activity on the Intel Cyclone 10 GX and Intel Arria 10 device transceiver pins." This statement is in the below link. "1.3.2. Transceiver Pin Guidance for Unpowered FPGA " page 14
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an692.pdf
Is it possible to correlate above statement with statement in an692?
With Regards,
HPB
Regular ContributorHello,
Yes. The first statement described the process during power-up and power-down while the second statement described about configuring for unpowered FPGA.
Thanks.
