Arria 10 FPGA single precision hardened DSP question

Hi, there,

This is Xin.

I download the Quartus II 14.0 for Arria10 series version and device support, hoping to see the difference after having hardened floating point core.

However, while I use the floating point IP within the IP catalog, either the "floating point hardware" or "floating point hardware 2", the synthesis result shows that the project still uses the traditional DSP rather than the floating point core.

My question is:

1. How to implement the application so that the synthesis will show the usage of the single precision floating point hardened cores?

2. In the compilation report, there are Analysis and synthesis DSP block usage summary. While using 'floating point hardware', the result is "Independent 18*18" is 4, "Sum of two 18*18" is 1. Those are fixed multipliers right? If floating point DSP is used, should the number of those kinds of DSP also show here?

3. Is there any project example available to try?

Thanks a lot!

anyone?