Arria 10 EMIF PLL reference clock I/O standard for DDR3L

Hi Sir,

Please accept my apology for misunderstanding your inquiry previously. Here is my latest reply.

1. I’m connecting DDR3L memory with 1,35 V power supply. On Arria 10 GX memory banks are supplied with 1,35 V. In Quartus 18 project there’s altera_emif module, witch has these settings on FPGA I/O tab:

- protocol: DDR3

- voltage: 1.35 V (DDR3L)

- PLL reference clock I/O standard: LVDS with On-Chip Termination.

Clock source has LVDS output and it’s connected to dedicated clock input in hard memory controller. Whole project compiles without errors, however I’m wondering:

- usually LVDS on Altera devices requires 1,8 V bank voltage to achieve common mode voltage Vcm=1,25 V. Here I have receiver in 1,35 V bank – is this still compatible with LVDS?

It’s NOT compatible with LVDS. Your receiver has to be 1.8V. If you want to interface between 1.8 V with 1.35 V then you may have to do DC bias at board level on your own.

2. My clock source cannot achieve Vcm=1,25 V, it has Vcm =0,9 V and 400 mVpp swing. Is it compatible with PLL refclk input on hard memory controller with LVDS input and 1,35 V bank supply?

Yes, it’s compatible but your Dmax need to be less than 700Mbps.

3. If there's no bias why Quartus generated IBIS model behaves like there’s one (with OCT enabled)? Also keep in mind, that we’re talking on hard memory controller, not LVDS I/O. It does not support LVPECL as clock source standard at all (emif in Quartus 18.0 Pro possible standards: LVDS OCT, LVDS no OCT, SSTL-135) . Hard memory controller input may be very different that standard I/O pll input. Also there was a discussion here https://forums.intel.com/s/feed/0D50P00003yyRRdSAM?language=en_US with conclusion that enabling OCT on LVDS will bias AC links. So I’m bit confused.

Yes sir, you are absolutely right that we do not support LVPECL in EMIF. What I meant before about the LVPECL is just a sharing.

Thanks

Regards,

NAli1