Arria 10 EMIF PLL reference clock I/O standard for DDR3L

Thanks for replay.

"LVDS input is power up by VCCPT which equal to 1.5V that is similar to all I/O standard. The output come from VCCIO which is 1.8V. You can refer to “Intel Arria 10 I/O Standards Voltage Levels” (page 104) for more details."

I see now that for input VCCPT matters, not VCCIO. So it will stick to the standard. To be exact VCCPT of Arria 10 is 1,8 V, not 1,5 V.

"Since you are using the LVDS input 1.5V, so you need to meet Vcm=1.25 V in order to meet the LVDS input volatage. This is the specification for Differential I/O Standards."

I'm not convinced by this because there's no toleration included. So how close one should be to 1,25 V Vcm? In Arria 10 datasheet on LVDS there’s an Vicm(DC) (V) that has min 0 V, max 1,85 V for lower data rate. Is this proper range for input common mode voltage for refclk in hard memory controller?

Also if you take a look on Arria 10 development boards it looks like there’s DC link from Silicon Labs clock source to hard memory controller. This kind of clock can’t achieve Vcm of 1,25 V with it’s power supply (however on development boards there are external terminations, so OCT is not used).

"As I mentioned before for LVDS I/O’s there is no internal bias. However for LVPECL AC-Coupled External Termination we do support termination with bias. For more details, you can refer to Arria 10 Handbook (page 147)".

f there's no bias why Quartus generated IBIS model behaves like there’s one (with OCT enabled)? Also keep in mind, that we’re talking on hard memory controller, not LVDS I/O. It does not support LVPECL as clock source standard at all (emif in Quartus 18.0 Pro possible standards: LVDS OCT, LVDS no OCT, SSTL-135) . Hard memory controller input may be very different that standard I/O pll input. Also there was a discussion here https://forums.intel.com/s/feed/0D50P00003yyRRdSAM?language=en_US with conclusion that enabling OCT on LVDS will bias AC links. So I’m bit confused.